rggen ☆
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Description:
Code generation tool for control and status registers
Type: Formula  |  Tracked Since: Dec 28, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: hardware fpga asic code-generation registers systemverilog
Install: brew install rggen
About:
Rggen is a code generation tool specifically designed for creating register access layers for control and status registers (CSRs) in hardware designs. It allows developers to define registers using a simple YAML or Ruby DSL, then automatically generates RTL code, software headers, and documentation. This significantly reduces manual coding errors and accelerates the development of hardware/software interfaces.
Key Features:
  • Multi-language output generation (SystemVerilog, VHDL, C, HTML, etc.)
  • Input formats: YAML, Ruby DSL, JSON, CSV
  • Plugin-based architecture for extensibility
  • Automated generation of software headers and documentation
Use Cases:
  • Generating register maps for FPGA/ASIC designs
  • Creating consistent software headers for firmware development
  • Automating documentation generation for hardware registers
Alternatives:
  • PeakRDL – Industry standard using SystemRDL input; Rggen uses simpler YAML/DSL inputs
  • reggen – Common in RISC-V ecosystems; Rggen is more generic and flexible
Version History
Detected Version Rev Change Commit
Sep 15, 2025 1:03pm 0 VERSION_BUMP 30a91b8a
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