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hardware
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verilog
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systemverilog
|
| Package |
Description |
Version |
|
netlistsvg
☆
formula
753
|
Draws an SVG schematic from a yosys JSON netlist |
1.0.2 |
|
bender
☆
formula
|
Dependency management tool for hardware projects |
0.29.1 |
|
bsc
☆
formula
|
Bluespec Compiler (BSC) |
2025.07 |
|
ghdl
☆
cask
|
VHDL 2008/93/87 simulator |
5.1.1 |
|
icestudio
☆
cask
|
Visual editor for open FPGA board |
0.12 |
|
logisim-evolution
☆
cask
|
Digital logic designer and simulator |
4.1.0 |
|
nvc
☆
formula
|
VHDL compiler and simulator |
|
|
openfpgaloader
☆
formula
|
Universal utility for programming FPGA |
|
|
prjtrellis
☆
formula
|
Documenting the Lattice ECP5 bit-stream format |
1.4 |
|
rggen
☆
formula
|
Code generation tool for control and status registers |
|
|
surfer
☆
formula
|
Waveform viewer, supporting VCD, FST, or GHW format |
0.4.0 |
|
yosys
☆
formula
|
Framework for Verilog RTL synthesis |
0.60 |