nvc ☆
« Back to VersTracker
Description:
VHDL compiler and simulator
Type: Formula  |  Tracked Since: Dec 28, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: vhdl simulation hardware-design eda compiler fpga
Install: brew install nvc
About:
Nvc is a VHDL compiler and simulator that translates VHDL code into an intermediate representation for execution. It provides a complete environment for developing and testing digital designs without requiring proprietary EDA tools. The tool supports significant portions of the VHDL standard, making it suitable for both educational and professional hardware design workflows.
Key Features:
  • VHDL-2008 language support
  • Built-in test framework with coverage analysis
  • LLVM-based code generation for performance
  • Interactive debugger and waveform viewer
  • Plugin architecture for custom extensions
Use Cases:
  • Digital circuit simulation and verification
  • VHDL code linting and static analysis
  • Automated testing of hardware designs in CI/CD
  • Educational purposes for learning VHDL and digital design
Alternatives:
  • GHDL – GHDL is another open-source VHDL simulator; Nvc offers better VHDL-2008 support and a more modern codebase
  • ModelSim – ModelSim is a commercial simulator with GUI; Nvc provides a free, command-line focused alternative
Version History
Detected Version Rev Change Commit
Sep 28, 2025 11:57pm 0 VERSION_BUMP 17586fb7
Sep 28, 2025 11:09pm 0 VERSION_BUMP 4f69e24d
Sep 16, 2025 3:44pm 1 VERSION_BUMP 65e09f40
Jan 11, 2025 4:15pm 0 VERSION_BUMP 97ff2db5
Oct 26, 2024 12:46pm 0 VERSION_BUMP a85ed24f
Sep 29, 2024 1:46pm 1 VERSION_BUMP 4120fce7
« Back to VersTracker  |  Browse Packages  |  About