Description:
VHDL compiler and simulator
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Type: Formula
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Tracked Since: Dec 28, 2025
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Links:
Homepage |
formulae.brew.sh
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Category: Developer tools
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Tags:
vhdl
simulation
hardware-design
eda
compiler
fpga
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Install:
brew install nvc
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About:
Nvc is a VHDL compiler and simulator that translates VHDL code into an intermediate representation for execution. It provides a complete environment for developing and testing digital designs without requiring proprietary EDA tools. The tool supports significant portions of the VHDL standard, making it suitable for both educational and professional hardware design workflows.
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Key Features:
- VHDL-2008 language support
- Built-in test framework with coverage analysis
- LLVM-based code generation for performance
- Interactive debugger and waveform viewer
- Plugin architecture for custom extensions
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Use Cases:
- Digital circuit simulation and verification
- VHDL code linting and static analysis
- Automated testing of hardware designs in CI/CD
- Educational purposes for learning VHDL and digital design
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Alternatives:
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GHDL
– GHDL is another open-source VHDL simulator; Nvc offers better VHDL-2008 support and a more modern codebase
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ModelSim
– ModelSim is a commercial simulator with GUI; Nvc provides a free, command-line focused alternative
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