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Related:
verilog
eda
fpga
systemverilog
compiler
vhdl
simulation
asic
bluespec
electronics
|
| Package |
Description |
Version |
|
bsc
☆
formula
|
Bluespec Compiler (BSC) |
2025.07 |
|
icestudio
☆
cask
|
Visual editor for open FPGA board |
0.12 |
|
nvc
☆
formula
|
VHDL compiler and simulator |
|
|
surelog
☆
formula
|
SystemVerilog Pre-processor, parser, elaborator, UHDM compiler |
1.86 |
|
sv2v
☆
formula
|
SystemVerilog to Verilog conversion |
|
|
svlint
☆
formula
|
SystemVerilog linter |
|
|
verilator
☆
formula
|
Verilog simulator |
|
|
yosys
☆
formula
|
Framework for Verilog RTL synthesis |
0.60 |