surelog ☆
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Description:
SystemVerilog Pre-processor, parser, elaborator, UHDM compiler
Type: Formula  |  Latest Version: 1.86@0  |  Tracked Since: Dec 18, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: systemverilog hardware-design eda uhdm parser verilog
Install: brew install surelog
About:
Surelog is a comprehensive SystemVerilog toolkit that handles preprocessing, parsing, and elaboration of hardware designs. It compiles designs into UHDM (Universal Hardware Data Model), providing a standardized representation for downstream tools. This enables robust design analysis, linting, and integration within modern EDA toolchains.
Key Features:
  • Full SystemVerilog IEEE 1800-2017 preprocessing and parsing
  • Elaboration of design hierarchy and generation of UHDM
  • Built-in linter and design rule checking capabilities
  • Support for industry-standard UVM testbench frameworks
Use Cases:
  • Preprocessing and parsing large SystemVerilog codebases
  • Generating UHDM for integration with other EDA tools
  • Performing static analysis and linting on hardware designs
Alternatives:
  • Verilator – Verilator is primarily a fast simulator, while Surelog focuses on parsing and UHDM generation for toolchain integration
  • Icarus Verilog – Icarus Verilog is a simpler interpreter, whereas Surelog provides a more complete SystemVerilog implementation with elaboration
Version History
Detected Version Rev Change Commit
Dec 18, 2025 8:06am 1.86 0 VERSION_BUMP e3892af5
Dec 21, 2024 11:51pm 1 VERSION_BUMP 85d3c517
Oct 11, 2024 7:20pm 0 VERSION_BUMP 4aa53007
Sep 13, 2024 9:10pm 0 VERSION_BUMP 31eb0d22
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