icarus-verilog ☆
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Description:
Verilog simulation and synthesis tool
Type: Formula  |  Tracked Since: Dec 28, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: verilog hdl simulation synthesis eda hardware
Install: brew install icarus-verilog
About:
Icarus Verilog is a Verilog simulation and synthesis tool that compiles Verilog code into various formats, including executable simulation models and netlists. It serves as a robust compiler backend for the Verilog hardware description language, enabling designers to simulate digital circuits before hardware implementation. The tool is widely used for its stability and support for a broad subset of the Verilog standard.
Key Features:
  • Compiles Verilog into executable simulation models
  • Supports synthesis to structural netlists
  • Portable and runs on multiple operating systems
  • Acts as a stable backend for other EDA tools
Use Cases:
  • Simulating digital logic designs for verification
  • Compiling Verilog for FPGA or ASIC synthesis workflows
  • Serving as a reference compiler for Verilog language development
Alternatives:
  • Verilator – Verilator compiles Verilog to C++/SystemC for high-performance simulation, whereas Icarus Verilog focuses on standard simulation and synthesis compilation.
  • GHDL – GHDL is an open-source VHDL simulator, serving a different hardware description language than Icarus Verilog's Verilog focus.
Version History
Detected Version Rev Change Commit
Sep 11, 2025 5:06am 0 VERSION_BUMP acdd4814
Dec 3, 2024 7:54pm 0 VERSION_BUMP a6f66a89
Feb 16, 2024 11:20am 0 VERSION_BUMP c5b4a842
Jun 11, 2023 1:38pm 0 VERSION_BUMP cb7c79ee
Mar 18, 2023 3:36am 0 VERSION_BUMP 26159482
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