Tag: verilog 12 packages with this tag
« Back to VersTracker  |  All Categories  |  All Tags  |  Related: eda hardware-design systemverilog electronics fpga simulation synthesis hardware visualization svg
Package Description Version
netlistsvg ☆ formula 753 Draws an SVG schematic from a yosys JSON netlist 1.0.2
bsc ☆ formula Bluespec Compiler (BSC) 2025.07
gplcver ☆ formula Pragmatic C Software GPL Cver 2001
gtkwave ☆ cask GTK+ based wave viewer 3.3.107
icarus-verilog ☆ formula Verilog simulation and synthesis tool
icestudio ☆ cask Visual editor for open FPGA board 0.12
surelog ☆ formula SystemVerilog Pre-processor, parser, elaborator, UHDM compiler 1.86
sv2v ☆ formula SystemVerilog to Verilog conversion
svlint ☆ formula SystemVerilog linter
svls ☆ formula SystemVerilog language server
verilator ☆ formula Verilog simulator
yosys ☆ formula Framework for Verilog RTL synthesis 0.60
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