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Related:
hardware
electronics
verilog
hardware-design
simulation
systemverilog
cad
vhdl
fpga
pcb-design
|
| Package |
Description |
Version |
|
eagle
☆
cask
|
Electronic design automation software |
9.6.2 |
|
easyeda2kicad
☆
formula
|
Converts electronic components from EasyEDA or LCSC to a KiCad library |
0.8.0 |
|
electricbinary
☆
cask
|
Electrical CAD system for the design of integrated circuits |
9.08.1 |
|
ghdl
☆
cask
|
VHDL 2008/93/87 simulator |
5.1.1 |
|
gplcver
☆
formula
|
Pragmatic C Software GPL Cver 2001 |
|
|
icarus-verilog
☆
formula
|
Verilog simulation and synthesis tool |
|
|
icestudio
☆
cask
|
Visual editor for open FPGA board |
0.12 |
|
kicad
☆
cask
|
Electronics design automation suite |
9.0.7 |
|
klayout
☆
cask
|
IC design layout viewer and editor |
0.27.13 |
|
libngspice
☆
formula
|
Spice circuit simulator as shared library |
|
|
librepcb
☆
cask
|
EDA software to develop printed circuit boards |
2.0.0 |
|
nvc
☆
formula
|
VHDL compiler and simulator |
|
|
pcb
☆
formula
|
Interactive printed circuit board editor |
|
|
sby
☆
formula
|
Front-end for Yosys-based formal verification flows |
0.60 |
|
surelog
☆
formula
|
SystemVerilog Pre-processor, parser, elaborator, UHDM compiler |
1.86 |
|
sv2v
☆
formula
|
SystemVerilog to Verilog conversion |
|
|
svlint
☆
formula
|
SystemVerilog linter |
|
|
svls
☆
formula
|
SystemVerilog language server |
|
|
systemc
☆
formula
|
Core SystemC language and examples |
3.0.2 |
|
uhdm
☆
formula
|
Universal Hardware Data Model, modeling of the SystemVerilog Object Model |
1.86 |
|
verilator
☆
formula
|
Verilog simulator |
|
|
yosys
☆
formula
|
Framework for Verilog RTL synthesis |
0.60 |