systemc ☆
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Description:
Core SystemC language and examples
Type: Formula  |  Latest Version: 3.0.2@0  |  Tracked Since: Oct 31, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: hardware simulation systemc modeling eda vhdl
Install: brew install systemc
About:
SystemC is a C++ library and event-driven simulation kernel used for modeling and simulating hardware systems at the transaction level. It enables the creation of virtual prototypes for performance analysis, architectural exploration, and early software development. This package provides the core language extensions and example models to get started with system-level design.
Key Features:
  • Event-driven discrete-event simulation kernel
  • C++ class libraries for concurrent process modeling
  • Support for abstract transaction-level modeling (TLM)
  • Interoperability with Verilog/VHDL via PLI interfaces
Use Cases:
  • Architectural exploration of System-on-Chip (SoC) designs
  • Performance analysis of complex hardware/software systems
  • Early firmware and driver development on virtual prototypes
Alternatives:
  • Verilator – Verilator compiles Verilog to C++/SystemC for fast simulation, whereas SystemC is a language extension for modeling at higher abstraction levels.
  • Chisel – Chisel is a Scala-based hardware construction language that generates Verilog, focusing on design generation rather than the simulation kernel provided by SystemC.
Version History
Detected Version Rev Change Commit
Oct 31, 2025 6:56pm 0 VERSION_BUMP bd4a2edc
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