Description:
Verilog simulator
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Type: Formula
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Tracked Since: Dec 28, 2025
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Links:
Homepage |
formulae.brew.sh
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Category: Developer tools
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Tags:
verilog
systemverilog
simulation
hardware-design
eda
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Install:
brew install verilator
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About:
Verilator is a high-performance, open-source Verilog/SystemVerilog simulator. It works by converting Verilog code into a C++ or SystemC model, which is then compiled for fast execution. Its primary value proposition is delivering cycle-accurate simulation speeds significantly faster than traditional event-driven simulators.
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Key Features:
- Generates highly optimized C++ or SystemC models
- Supports SystemVerilog assertions and limited synthesis constructs
- Includes built-in linting capabilities for code quality checks
- Free and open-source with active community support
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Use Cases:
- Functional verification of digital logic designs
- Performance acceleration for hardware/software co-design
- Running large-scale testbenches where speed is critical
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Alternatives:
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Icarus Verilog
– More lightweight and standards-compliant, but generally slower for large designs.
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VCS / ModelSim
– Commercial simulators offering full language support and GUIs, but at a significant cost.
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