verilator ☆
« Back to VersTracker
Description:
Verilog simulator
Type: Formula  |  Tracked Since: Dec 28, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: verilog systemverilog simulation hardware-design eda
Install: brew install verilator
About:
Verilator is a high-performance, open-source Verilog/SystemVerilog simulator. It works by converting Verilog code into a C++ or SystemC model, which is then compiled for fast execution. Its primary value proposition is delivering cycle-accurate simulation speeds significantly faster than traditional event-driven simulators.
Key Features:
  • Generates highly optimized C++ or SystemC models
  • Supports SystemVerilog assertions and limited synthesis constructs
  • Includes built-in linting capabilities for code quality checks
  • Free and open-source with active community support
Use Cases:
  • Functional verification of digital logic designs
  • Performance acceleration for hardware/software co-design
  • Running large-scale testbenches where speed is critical
Alternatives:
  • Icarus Verilog – More lightweight and standards-compliant, but generally slower for large designs.
  • VCS / ModelSim – Commercial simulators offering full language support and GUIs, but at a significant cost.
Version History
Detected Version Rev Change Commit
Sep 16, 2025 1:41am 0 VERSION_BUMP 9af5da0d
Jan 1, 2025 2:40pm 0 VERSION_BUMP 3e62fe63
Jan 1, 2025 2:13pm 0 VERSION_BUMP 2201d1be
Oct 27, 2024 3:51pm 0 VERSION_BUMP 55766c70
« Back to VersTracker  |  Browse Packages  |  About