yosys
« Back to VersTracker
Description:
Framework for Verilog RTL synthesis
Type: Formula  |  Latest Version: 0.60@0  |  Tracked Since: Nov 11, 2025
Links: Homepage  |  @YosysHQ  |  formulae.brew.sh
Category: Developer tools
Tags: verilog synthesis fpga rtl eda hardware-design
Install: brew install yosys
About:
Yosys is a powerful open-source framework for Verilog RTL synthesis. It performs high-level synthesis tasks, converting Verilog code into gate-level representations suitable for FPGA or ASIC implementation. Its modular architecture and extensive Python API make it a cornerstone of modern open-source digital design flows.
Key Features:
  • Verilog 2005/2012 parser with synthesis capabilities
  • Extensible architecture via YosysIL (intermediate language)
  • Built-in formal verification methods (SMT, BMC)
  • Rich scripting interface (Yosys shell and Python API)
  • Broad support for standard cell libraries and FPGA architectures
Use Cases:
  • Compiling Verilog designs for open-source FPGA toolchains (e.g., IceStorm, Trellis)
  • Performing logic equivalence checking between RTL and gate-level netlists
  • Exploring and optimizing gate-level netlists for performance or area
  • Building custom synthesis flows for research or EDA development
Alternatives:
  • Verilator – Verilator is primarily a fast Verilog simulator (cycle-based), whereas Yosys focuses on logic synthesis and formal verification.
  • Commercial EDA Suites (e.g., Vivado, Quartus) – Yosys is open-source and scriptable, offering transparency and flexibility, while commercial tools provide highly optimized vendor-specific flows and GUI integration.
Version History
Detected Version Rev Change Commit
Nov 11, 2025 5:30pm 0 VERSION_BUMP bd934c4e
Nov 11, 2025 12:08pm 0 VERSION_BUMP 152397fc
Dec 14, 2024 10:18pm 0 VERSION_BUMP 0572c7c9
Nov 20, 2024 1:16pm 1 VERSION_BUMP 3769cbf1
Nov 10, 2024 1:46pm 1 VERSION_BUMP 24a23c12
Nov 10, 2024 10:15am 1 VERSION_BUMP f2f916cf
Oct 13, 2024 8:05pm 0 VERSION_BUMP 7c0060ac