Description:
Framework for Verilog RTL synthesis
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Type: Formula
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Latest Version: 0.60@0
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Tracked Since: Nov 11, 2025
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Links:
Homepage |
@YosysHQ |
formulae.brew.sh
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Category: Developer tools
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Tags:
verilog
synthesis
fpga
rtl
eda
hardware-design
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Install:
brew install yosys
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About:
Yosys is a powerful open-source framework for Verilog RTL synthesis. It performs high-level synthesis tasks, converting Verilog code into gate-level representations suitable for FPGA or ASIC implementation. Its modular architecture and extensive Python API make it a cornerstone of modern open-source digital design flows.
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Key Features:
- Verilog 2005/2012 parser with synthesis capabilities
- Extensible architecture via YosysIL (intermediate language)
- Built-in formal verification methods (SMT, BMC)
- Rich scripting interface (Yosys shell and Python API)
- Broad support for standard cell libraries and FPGA architectures
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Use Cases:
- Compiling Verilog designs for open-source FPGA toolchains (e.g., IceStorm, Trellis)
- Performing logic equivalence checking between RTL and gate-level netlists
- Exploring and optimizing gate-level netlists for performance or area
- Building custom synthesis flows for research or EDA development
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Alternatives:
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Verilator
– Verilator is primarily a fast Verilog simulator (cycle-based), whereas Yosys focuses on logic synthesis and formal verification.
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Commercial EDA Suites (e.g., Vivado, Quartus)
– Yosys is open-source and scriptable, offering transparency and flexibility, while commercial tools provide highly optimized vendor-specific flows and GUI integration.
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