| Tag: rtl 2 packages with this tag | ||
| « Back to VersTracker | All Categories | All Tags | Related: unicode text-processing bidirectional library cli verilog synthesis fpga eda hardware-design | ||
| Package | Description | Version |
|---|---|---|
| fribidi ☆ formula | Implementation of the Unicode BiDi algorithm | |
| yosys ☆ formula | Framework for Verilog RTL synthesis | 0.60 |