svls ☆
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Description:
SystemVerilog language server
Type: Formula  |  Tracked Since: Dec 28, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: systemverilog verilog lsp hardware eda
Install: brew install svls
About:
svls is a SystemVerilog language server that provides IDE features like code completion, diagnostics, and go-to-definition for hardware design. It leverages the sv-parser library to accurately parse and analyze Verilog and SystemVerilog source files, enabling rich editor integration via the Language Server Protocol.
Key Features:
  • LSP (Language Server Protocol) implementation
  • Real-time syntax checking and diagnostics
  • Code completion and go-to-definition support
  • SystemVerilog 2017 standard compliance
Use Cases:
  • Hardware design and verification in SystemVerilog
  • IDE integration for Verilog development
Alternatives:
  • verible – Verible offers similar LSP features but is implemented in C++ and maintained by Google
  • icarus-verilog – Icarus Verilog is a simulator rather than a language server, focusing on compilation and simulation
Version History
Detected Version Rev Change Commit
Sep 13, 2025 6:41am 0 VERSION_BUMP 31144c56
Sep 13, 2024 12:37am 0 VERSION_BUMP f3603bc9
Nov 19, 2023 10:45pm 0 VERSION_BUMP 7ca11d2c
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