uhdm ☆
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Description:
Universal Hardware Data Model, modeling of the SystemVerilog Object Model
Type: Formula  |  Latest Version: 1.86@0  |  Tracked Since: Dec 18, 2025
Links: Homepage  |  formulae.brew.sh
Category: Developer tools
Tags: eda systemverilog hardware uhdm vlsi
Install: brew install uhdm
About:
UHDM is a C++ library that provides a complete, implementation-agnostic representation of the SystemVerilog Object Model. It serves as a standardized interchange format for pre-processed SystemVerilog designs, enabling tools to communicate without needing their own parsers. Its primary value is in decoupling front-end parsers from analysis and synthesis back-ends in the EDA toolchain.
Key Features:
  • Provides a complete, serialized representation of SystemVerilog designs
  • Acts as a stable API for tool interoperability
  • Supports both standard SystemVerilog constructs and custom extensions
  • Enables separation of front-end parsing from back-end processing
Use Cases:
  • Building custom EDA tools for design analysis or verification
  • Interfacing between front-end parsers (like Surelog) and synthesis/verification back-ends
  • Enabling vendor-neutral data exchange for hardware design models
Alternatives:
  • Surelog – Surelog is a parser that generates UHDM; they are complementary parts of the same toolchain.
  • liberty – Liberty is for timing models, not the full structural design object model.
Version History
Detected Version Rev Change Commit
Dec 18, 2025 8:06am 1.86 0 VERSION_BUMP 1323ecd5
Oct 11, 2025 11:20am 0 VERSION_BUMP a05abda2
Sep 11, 2025 11:06am 0 VERSION_BUMP 0b7842ff
Dec 21, 2024 11:51pm 1 VERSION_BUMP 795b0adf
Oct 11, 2024 7:20pm 0 VERSION_BUMP 1ab81cd9
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